Constructing a chip package, e.g. a chip housing, may be challenging when the number of chips within a circuit is large. Chip housings may be provided for the packaging of one or more semiconductor chips, for example, if more than one power semiconductor chip or one or more logic integrated circuit chips are to be packaged as a single device. Traditionally, chip-on-chip construction may be used for the formation of multiple chip housings. For example, a back side of a logic integrated circuit chip may be glued to an electrically insulating medium over a side of the power semiconductor chip. Therefore, a logic integrated circuit chip may be attached to a power semiconductor chip over a shared die pad. The logic integrated circuit chip may be electrically insulated from the die pad and the power semiconductor chip. However, when more than one power semiconductor chip and one or more logic integrated chips are to be constructed in a housing, each chip may be packaged individually in a separate housing, and then electrically connected with each other over a single lead frame. Another option is a costly double copper bonded based housing wherein a plurality of power semiconductor chips with vertical current may each be bonded separately onto a separate metal layers, e.g. copper layers, onto a ceramic. The logic integrated circuit chips may either be fixed to another side of the ceramic side, or fixed onto, but electrically isolated from the separate metal layers.